Job Description

San Jose, CA (ONSITE or HYBRID 2/3 days in office)

Reports to: VP of Information Technology

Recruiter contact: cathy@recruiterhustle(dot)com

If you're interested in hearing more about this opportunity, feel free to email your resume to the lead recruiter handling this search. Cathy@recruiterhustle(dot)com We looking forward in connecting with you!

Opportunity Highlights

We have partnered with a $50M technology company in the San Jose, CA area and is seeking a Corporate Application Engineer. Our client helps enable engineering and design teams at the world’s most transformative brands to connect and integrate today’s system-on-chips (SoCs) that fuel modern innovation.

Duties:

• Lead Architect for Field AE Organization: Collaborate with the engineering team and the CTO's office to become the primary technical resource for the Field Application Engineer (FAE) organization.
• Drive Customer Adoption: Negotiate requirements with customers to promote the adoption of our products in leading-edge chip designs.
• Market and Customer Understanding: Gain deep understanding of customer and prospect designs, identifying their challenges and providing guidance to the CTO's office and engineering team to ensure developments align with market needs.
• Technical Solution Delivery: Partner with a team of experts to deliver and support interconnect and memory hierarchy solutions for complex mobile, telecom, automotive, AI, and consumer SoC designs.
• Technical Pre-Sales: Leverage your expertise in system design, SoC architecture, and RTL, along with your passion for technology, to participate in pre-sales activities and convince potential customers of the technical merits of your solutions.
• Post-Sales Support: Participate in post-sales support for some of the most innovative and advanced customers in the semiconductor industry.
• Technical Content Creation: Develop application notes and white papers to provide valuable technical information.
• FAE Training: Design and deliver training programs to educate the FAE organization on new solutions.

Experience:

• 10+ years of relevant front-end digital ASIC design experience, encompassing the entire flow from RTL design to synthesis.
• Minimum 5 years of experience in designing complex System-on-Chip (SoC) architectures.
• In-depth understanding of multi-CPU subsystem architecture, cache coherency protocols, and memory hierarchies.
• Solid understanding of SoC system-level architectures.
• Experience with CPU integration, bus fabrics, and DDR interfaces.
• Familiarity with the ARM ecosystem, including CPUs, GPUs, and other components.

Technical Skills:

• Proven experience with RTL synthesis tools (e.g., DC, DC-topo, RTLA, Fusion Compiler).

Soft Skills:

• Customer-focused with a strong desire to collaborate and find solutions.
• Experience working directly with customers or alongside a sales team.
• Highly motivated, with excellent problem-solving and results-driven approach.
• Strong presentation and organizational skills.
• Passionate about mentoring and guiding others through complex challenges.
• Team player with the ability to take initiative.

Travel:

• Approximately 10% travel within North America (USA and Canada) required.

Education Requirements:

• BS/MS in Electrical Engineering

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